Spur reducing architecture of frequency synthesiser using switched capacitors
Spur reducing architecture of frequency synthesiser using switched capacitors
About this item
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Author / Creator
Publisher
Stevenage: The Institution of Engineering and Technology
Journal title
Language
English
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Publication information
Publisher
Stevenage: The Institution of Engineering and Technology
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Scope and Contents
Contents
This study presents a new spur reducing architecture of phase-locked loop-based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi-spaced time intervals. It reduces fundamental a...
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Full title
Spur reducing architecture of frequency synthesiser using switched capacitors
Authors, Artists and Contributors
Author / Creator
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Record Identifier
TN_cdi_iet_journals_10_1049_iet_cds_2013_0200
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_iet_journals_10_1049_iet_cds_2013_0200
Other Identifiers
ISSN
1751-858X,1751-8598
E-ISSN
1751-8598
DOI
10.1049/iet-cds.2013.0200
