Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology...
Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology approach
About this item
Full title
Author / Creator
Publisher
London: Springer London
Journal title
Language
English
Formats
Publication information
Publisher
London: Springer London
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Scope and Contents
Contents
The stress concentration and deformation of the 3D stacked IC structures can be minimized with an optimal design of the integrated circuit (IC) using a response surface methodology. The geometrical and process parameters (i.e.,
A
= inlet pressure,
B
= solder bump standoff height,
C
= chip thickness, and
D
= aspect ratio) wer...
Alternative Titles
Full title
Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology approach
Authors, Artists and Contributors
Author / Creator
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Primary Identifiers
Record Identifier
TN_cdi_proquest_journals_2490878853
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_journals_2490878853
Other Identifiers
ISSN
0268-3768
E-ISSN
1433-3015
DOI
10.1007/s00170-019-03525-4
