Design of tunnel FET architectures for low power application using improved Chimp optimizer algorith...
Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm
About this item
Full title
Author / Creator
Publisher
London: Springer London
Journal title
Language
English
Formats
Publication information
Publisher
London: Springer London
Subjects
More information
Scope and Contents
Contents
An improved Chimps optimizer algorithm is proposed in this paper and is applied for the performance optimization of tunnel FET architectures for use in low power VLSI circuits. The steep subthreshold characteristics of TFET improves device performance and make it suitable for low power digital and memory applications. Classical Chimps optimizer has...
Alternative Titles
Full title
Design of tunnel FET architectures for low power application using improved Chimp optimizer algorithm
Authors, Artists and Contributors
Author / Creator
Identifiers
Primary Identifiers
Record Identifier
TN_cdi_proquest_journals_2807222231
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_journals_2807222231
Other Identifiers
ISSN
0177-0667
E-ISSN
1435-5663
DOI
10.1007/s00366-021-01530-4
