Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
About this item
Full title
Author / Creator
Hur, J.Y. , Stefanov, T. , Wong, S. and Goossens, K.
Publisher
Stevenage: Institution of Engineering and Technology
Journal title
Language
English
Formats
Publication information
Publisher
Stevenage: Institution of Engineering and Technology
Subjects
More information
Scope and Contents
Contents
Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in field-programmable gate arrays (FPGA). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors presen...
Alternative Titles
Full title
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Authors, Artists and Contributors
Author / Creator
Identifiers
Primary Identifiers
Record Identifier
TN_cdi_proquest_miscellaneous_1651381636
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_miscellaneous_1651381636
Other Identifiers
ISSN
1751-8601
E-ISSN
1751-861X
DOI
10.1049/iet-cdt.2010.0105
