Four-valued memory circuit using three- peak MOS-NDR devices and circuits
Four-valued memory circuit using three- peak MOS-NDR devices and circuits
About this item
Full title
Four-valued memory circuit using three- peak MOS-NDR devices and circuits
Author / Creator
GAN, K.-J , CHEN, Y.-H , TSAI, C.-S and SU, L.-X
Publisher
London: Institution of Electrical Engineers
Journal title
Electronics letters, 2006-04, Vol.42 (9), p.514-515
Language
English
Formats
Publication information
Publisher
London: Institution of Electrical Engineers
Subjects
More information
Scope and Contents
Contents
A four-valued memory circuit using the three-peak MOS-NDR circuit as the driver and a current source as the load is demonstrated. The fabrication of the circuit is based on the standard 0.35mum CMOS process.
Alternative Titles
Full title
Four-valued memory circuit using three- peak MOS-NDR devices and circuits
Authors, Artists and Contributors
Author / Creator
Identifiers
Primary Identifiers
Record Identifier
TN_cdi_proquest_miscellaneous_29831476
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_miscellaneous_29831476
Other Identifiers
ISSN
0013-5194
E-ISSN
1350-911X
DOI
10.1049/el:20063634
