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Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test acc...

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test acc...

https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_miscellaneous_31924736

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism[Note 1]

About this item

Full title

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism[Note 1]

Publisher

Stevenage: Institution of Engineering and Technology

Journal title

IET computers & digital techniques, 2007-05, Vol.1 (3), p.197-206

Language

English

Formats

Publication information

Publisher

Stevenage: Institution of Engineering and Technology

More information

Scope and Contents

Contents

A new core test wrapper design approach is proposed, which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip to transport test data to embedded cores,...

Alternative Titles

Full title

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism[Note 1]

Authors, Artists and Contributors

Identifiers

Primary Identifiers

Record Identifier

TN_cdi_proquest_miscellaneous_31924736

Permalink

https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_proquest_miscellaneous_31924736

Other Identifiers

ISSN

1751-8601

E-ISSN

1751-861X

DOI

10.1049/iet-cdt:20060152

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