Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
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Publisher
London: Nature Publishing Group UK
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Language
English
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Publisher
London: Nature Publishing Group UK
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Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. I...
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Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
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TN_cdi_doaj_primary_oai_doaj_org_article_3aba0caa895f420b8b71b17ac1ba4519
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https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_doaj_primary_oai_doaj_org_article_3aba0caa895f420b8b71b17ac1ba4519
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ISSN
2045-2322
E-ISSN
2045-2322
DOI
10.1038/s41598-017-04055-3
