Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Desi...
Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits
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Publisher
Hoboken: Hindawi
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Language
English
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Hoboken: Hindawi
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Contents
When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this si...
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Full title
Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits
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TN_cdi_doaj_primary_oai_doaj_org_article_8726da12cd4744b2b60e5b82ffd88aa8
Permalink
https://devfeature-collection.sl.nsw.gov.au/record/TN_cdi_doaj_primary_oai_doaj_org_article_8726da12cd4744b2b60e5b82ffd88aa8
Other Identifiers
ISSN
1076-2787
E-ISSN
1099-0526
DOI
10.1155/2022/8658770
